Digital circuits include circuit elements whose input signals are synchronized using one or more clocks. Between these synchronizing elements may be multiple stages of logic that perform the desired computation. The propagation delay of a signal through this logic must meet certain requirements such that the synchronizing elements are able to capture the correct data at the intended clock stage, e.g., the rising or falling edge of the clock. If, for some reason, the signal is delayed through this logic and does not arrive at the synchronizing element by the required time period, a timing error may result, which may impair operation of the digital circuit.
Where the delay is known, the digital circuit may be designed to incorporate the delay. There are many variations, both static and dynamic, however, which cause delays to change in digital circuits. A process variation may result from the fabrication of the circuit. This static variation may affects the speed at which the circuit operates. Dynamic variations, such as reliability degradation, voltage and temperature fluctuations, and delay push-out due to crosstalk or noise, may be more difficult to predict and account for in a circuit design.
Typically, variations that cause delays in digital circuits are managed by “margining” the circuit, or changing its operating environment so as to avoid the delay condition. As one example, the clock frequency of the circuit may be sufficiently reduced so that the circuit works even under the worst-case variations. Even where the delay variation, such as a voltage droop, is infrequent, the slower clock rate ensures that the digital circuit does not experience a timing error. Another method of margining the circuit may be to increase the voltage supplied to the circuit.
Margining is undesirable because the full benefit of the original circuit design, in terms of power efficiency and speed, is not realized. Furthermore, margining does not always work. As variations increase, the margins are increasing as well, resulting in lower performance or higher power demands. In some circumstances, the variations may be difficult to accurately predict.
Another technique for addressing timing errors may be to operate the digital circuit according to its original design specifications and detect the worst-case condition. Thus, for example, the digital circuit may be maintained at a higher, “non-safe” frequency, that is, vulnerable to variations, but may include additional circuitry to detect the delay variation. Various methods have been proposed for detecting timing errors in digital circuits. One technique employs double-sampling flip-flops to detect when an input signal to the flip-flop arrives late, causing an error. If the later sampling does not match the original sampling, the data has arrived too late to be captured by the flip-flop, and an error is signaled. The error may then be handled by stalling the pipeline of the signal path and re-initiating the signal, for example. The double-sampling technique involves a large amount of overhead in terms of clocking power and circuit area.
Thus, there is a continuing need to provide a method and a system for detecting timing errors in a digital circuit that overcomes the shortcomings of the prior art.